undefined clock in synthesis

The read during write output is referring to the build options for an output register. That is not related to a memory megafunction failing. I assume you want output registers, and that is not the first thing to worry about.

The first step I would take a look at is your simulation stimulus signals. Since you are debugging in simulation, (good job) you are likely building your own reference clock. Take a look in simulation at the clock in the context (scope) of the test bench. Make sure it is working at the top level before it gets to the megafunction. Once that is working, follow it down through the heirarchy until it goes X.