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Altera_Forum's avatar
Altera_Forum
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18 years ago

undefined clock in synthesis

Hi, so i created a ram block in Quartus with megafunction wizzard. It is a 2-port MK4, i set it to auto, but it came out to be MK4. So it has one read, one write port, wren, clk, and addresses fo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

well, what actually happened is that one component was not bound and somehow modelsim did not catch that in source, but once i fixed that and resynthesized, clock was ok. Also another thing is that i synthesize ram since it's FPGA internal, every time i update memory init. file i have to resythesize it.