Unconstrained array of unconstrained records, VHDL-2008, Quartus Prime 16.0.0

Hi,

I am trying to use VHDL-2008 in Quartus Prime 16.0.0

I have a package with declaration of unconstrained array of unconstrained records type:

   type packet_uinstr_t is record
      src_col        :  std_logic_vector; --! address to GMII buffer, src_row is implicit  (position in the signal itself) (MSB in MVB)
      dst_row        : std_logic_vector; --! address to PCIE buffer
      dst_col        : std_logic_vector; --! address to PCIE buffer
      barrier_flag   : std_logic_vector; --! barrier flag, probably just std_logic (LSB in MVB)
   end record;

Then I have entity with this type:

   RX_PACKET_UINSTRS          : in  packet_uinstrs_t(0 to INPUT_ROWS-1)(src_col(log2(INPUT_COLS)-1 downto 0),
                                    dst_row(log2(OUTPUT_ROWS)-1 downto 0), dst_col(log2(OUTPUT_COLS)-1 downto 0),
                                    barrier_flag(BARRIER_WIDTH-1 downto 0));

In synthesis I get this error:

Error (10410): VHDL Type Conversion error at planner_ent.vhd(80): Type Conversion near text or symbol "packet_uinstr_t" must have one argument

I already specified VHDL-2008 in "Compiler Setting/VHDL Input" and in Files/Properties/HDL version for each file.

Question: Is this construct supported in Quartus Prime? This very same code is perfectly fine with Modelsim.

Thanks for any info...

[SOLVED]

in Quartus Prime PRO 16.0 it's perfectly working...