Forum Discussion
RHenr
Occasional Contributor
2 years agoUnable to use Avalon-MM master verification BFM in Questa sim
Hello, I have a bug similar to the one reported here : https://community.intel.com/t5/Intel-Quartus-Prime-Software/Avalon-Verification-IP-example-avlmm-1x1-vhdl-not-working-in/m-p/1516388 I tried ...
IgorKa
Occasional Contributor
2 years agoHello.
The problem is that the QuestaSim optimizer flashes the delta-events. If you are using multilanguage QuestaSim, the solution is to make little tunning in the "altera_avalon_mm_master_bfm_vhdl_wrapper.sv" file:
1) Change timescale resolution `timescale 1ps / 1ps
2) In line 519 add "#1", like:
always @(mm_master.signal_all_transactions_complete) begin
events[MM_MSTR_EVENT_ALL_TRANSACTIONS_COMPLETE] = 1;
#1 events[MM_MSTR_EVENT_ALL_TRANSACTIONS_COMPLETE] <= 0;
end
It will solve the problem. You can save the custom file and each Platform Design reconfiguration, just replace the "altera_avalon_mm_master_bfm_vhdl_wrapper.sv" file with a patched one.
Good Luck
Igor