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AKuma235's avatar
AKuma235
Icon for New Contributor rankNew Contributor
6 years ago

Unable to simulate GPIO DDR on modelsim 10.1d version.

It is showing that 'fiftyfivenm_ff' is missing. How to resolve this issue . Please help

C:/altera/13.1/modelsim_ase/altera/verilog/twentynm

# C:/altera/13.1/modelsim_ase/altera/vhdl/altera

# C:/altera/13.1/modelsim_ase/altera/verilog/220model

# C:/altera/13.1/modelsim_ase/altera/verilog/altera_lnsim

# C:/altera/13.1/modelsim_ase/altera/verilog/altera_mf

# C:/altera/13.1/modelsim_ase/altera/verilog/altera

# C:/altera/13.1/modelsim_ase/altera/verilog/max

# C:/altera/13.1/modelsim_ase/altera/verilog/220model

# C:/altera/13.1/modelsim_ase/altera/verilog/maxii

# F:/goldn_pen/Golden_Pen_Top_iputf_libs/DDR_Data

# F:/goldn_pen/rtl_work

# C:/altera/13.1/modelsim_ase/verilog

# C:/altera/13.1/modelsim_ase/modelsim_lib

# C:/altera/13.1/modelsim_ase/altera/verilog/twentynm

# C:/altera/13.1/modelsim_ase/altera/vhdl/altera

# F:/goldn_pen/Golden_Pen_Top_iputf_libs/DDR_Data

# ** Error: (vsim-3033) F:/goldn_pen/*/*/DDR_Data_sim/altera_gpio_lite/altera_gpio_lite.sv(743): Instantiation of 'fiftyfivenm_ff' failed. The design unit was not found.

Thanks

5 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    What are the full command that you use the vsim?

    Usually this happened if you did not specify the libraries.

    E.g. vsim -L stratixV....

  • AKuma235's avatar
    AKuma235
    Icon for New Contributor rankNew Contributor
    6 years ago

    Before giving simulation command on my testbench, I am adding all Verilog ​library i.e altera_ver, altera_mf_ver, altera_insim_ver and max_ver ;

    It is showing error of "fiftyfivenm_ff failed".

    I am using GUI for simulation and adding library into library option of pop up window for simulation.

    Thanks

  • AKuma235's avatar
    AKuma235
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    above youtube link helped me but the problem with DDR simulation still same. I was trying create new project in modelsim and run simulation after adding relevant libraries but I am getting same error both the way i.e. Nativelink or modelsim.

    vsim -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L ddr_module -L DDR_Data -voptargs=\"+acc\" -t 1ps work.t2

    # vsim -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L ddr_module -L DDR_Data -voptargs=\"+acc\" -t 1ps work.t2

    # Loading std.standard

    # Loading std.textio(body)

    # Loading ieee.std_logic_1164(body)

    # Loading ieee.std_logic_arith(body)

    # Loading work.t2(simltn)

    # Loading work.test2(behaviour)

    # Loading ieee.numeric_std(body)

    # Loading work.ddr_module(rtl)

    # ** Error: (vsim-19) Failed to access library 'fiftyfivenm' at "fiftyfivenm".

    #

    # No such file or directory. (errno = ENOENT)

    # ** Error: (vsim-19) Failed to access library 'fiftyfivenm_ver' at "fiftyfivenm_ver".

    #

    # No such file or directory. (errno = ENOENT)

    I tried in VHDL coding and just added one IP i.e DDR and have done simulation and above error it occurred.

    Thanks