Unable to simulate designs comprising FFT (ModelSim Intel FPGA Starter Edition 10.5b and 10.6d)

To get this design to simulate correctly , you need to compile the following files in order.

1. From the /simulation folder - the top-level fft design .v file

2. From the /simulation/submodules folder –

a. All of the _pkg.vhd files first

b. Then the _roundsat.vhd file

c. Followed by the rest of the .vhd files

3. Next, compile the files in the /simulation/submodules/mentor folder-

a. The Verilog files (there are only 2 of them)

b. All of the pkg files first

c. Then the apn_* VHDL files

d. Followed by the asj_* VHDL files -> except the asj_fft_sglstream. This one needs to be compiled last.

e. Next compile the rest of the files auk_* VHDL

f. Lastly compile the asj_fft_sglstream.vhd file.

4. All of the files should be compiled successfully and you should be able to see them in the work folder.

Now simulate the top-level module of the design or testbench. It will load successfully