Unable to read data from h2f_master port from HPS linux

HI Manikanta123

In the linux program that you are using how are you reading the memory mapped address?

What address value that you are reading from?

Regards

Jingyang, Teh

Hi Manikanta

Could you try to the command "md <address> <value" to read the memory in uboot?

To check if there are value in the memory region consist of value.

1. Boot the board.
2. Stop the boot flow at uboot.
3. Flash the FPGA sof file.
4. Enter the command "bdige enable" in uboot.
5. Enter the command "md <address> <count>"

Regards

Jingyang,Teh

Hai Jingyang,

Thanks for the reply. we tried as you suggested with above steps but the result is same i.e not showing any values in that address .

I checked after linux boot with devmem command also.

Here i attached the steps in u-boot console.

But the same flow is working fine in xilinx board ,i'm able read the data from that address .

Regards,

Manikanta

Hi Manikanta

Could you send us a screenshot of the parameters set in regarding the AXI for both HPS and the AXI4lite port?

Regards

Jingyang, Teh

Hai Jingyang,

Please find the screenshorts of HPS parameters ,Address map editor and custom axi-lite ip (rx-gen) parameters.

Regards,

Manikanta

Hi Manikanta

Did you happened to change your qsys design?

I see that the offset address for the IP have changed from 0xd0000 to 0x70000.

Could you try reading the address with offset 0x70000 using the md tool?

If it still cant be read, it seems like you will need to create a custom IP to convert the AXI4 signals to match with AXI4lite.

Unfortunately intel do not have an IP to do the conversion.

However you could try adding an AXI Bridge in between the HPS and the custom IP to see if we could work around this.

With the AXI Bridge there are some additional parameters that you could toggle on/off.

In the master connection, we could turn on the sideband signals to match the HPS and in the slave connection we could do the same to match the custom IP.

You could try toggling between the AXI4 and AXI4lite in the drop down menu as a reference to what signals are required for AXI4lite.

Regards

Jingyang, Teh

Hi

Any update on this forum?

Regards

Jingyang, Teh

Hai Jingyang,

We tried as u suggested with Axi bridges in between the IP's but the same issue i.e (rx_gen) is sending always zeros to HPS.

The read channel of rx-gen axi lite ip is always zeros but valid signal are high.

Thanks & Regards,

Manikanta

Hi Manikanta

Sorry for the wrong information regarding adding an axi bridfe.

The AXI4 master could be connected to the AXI4lite directly and qsys interconnect will connect them together.

Could you try adding a signalTap to capture the signals from AXI4 master and also the AXI4lite slave?

Signals to be look are ACLK,ARADDR,ARVALID,ARREADY,RDATA,RVALID,RREADY & RRESP

Another thing is could you try adding a master jtag and verify the register using systemConsole that the register during run time is having any values?

Regards

Jingyang, Teh

Hi Manikanta

Could you try reading the address map using system console?

You could try adding a jtag master in your qsys design and launching the system console from quartus.

What are the value that you are expecting?

Regards

Jingyang, Teh