Forum Discussion
tehjingy_Altera
Regular Contributor
3 years agoHi Manikanta
Sorry for the wrong information regarding adding an axi bridfe.
The AXI4 master could be connected to the AXI4lite directly and qsys interconnect will connect them together.
Could you try adding a signalTap to capture the signals from AXI4 master and also the AXI4lite slave?
Signals to be look are ACLK,ARADDR,ARVALID,ARREADY,RDATA,RVALID,RREADY & RRESP
Another thing is could you try adding a master jtag and verify the register using systemConsole that the register during run time is having any values?
Regards
Jingyang, Teh