New Contributor
Regular ContributorHi Manikanta
Sorry for the wrong information regarding adding an axi bridfe.
The AXI4 master could be connected to the AXI4lite directly and qsys interconnect will connect them together.
Could you try adding a signalTap to capture the signals from AXI4 master and also the AXI4lite slave?
Signals to be look are ACLK,ARADDR,ARVALID,ARREADY,RDATA,RVALID,RREADY & RRESP
Another thing is could you try adding a master jtag and verify the register using systemConsole that the register during run time is having any values?
Regards
Jingyang, Teh
New ContributorHai Jingyang,
We already check this signals ACLK,ARADDR,ARVALID,ARREADY,RDATA,RVALID,RREADY & RRESP in signal tap but ARADDR,ARVALID,ARREADY signals are high but the data from flowing through RDATA pin is always zero.
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