Unable to generate simulation files for avalon memory mapped read, write and slave IP

Then that means whatever these components are, they do not have simulation models available for them.

If these are your own custom components, they need to have Verilog simulation model files specified in the Component Editor when the component is created for this to work. You can specify the same design files should be used for both synthesis and simulation, but if no simulation model files are specified, you'll get these errors.