Forum Discussion
UART receiver loopback characters VHDL
- 3 years ago
Hi Tex,
You may check on this first example design link:
https://github.com/Domipheus/UART
https://domipheus.com/blog/a-uart-implementation-in-vhdl/
Make appropriate connection between O_tx and I_rx to form a loopback. The simulation result like below:
This is second example design link (apparently state machine):
https://nandland.com/project-7-uart-part-1-receive-data-from-computer/
https://www.edaplayground.com/x/7Em
https://www.edaplayground.com/x/5vEh
https://nandland.com/7-segment-display/
Make appropriate connection between o_TX_Serial and i_RX_Serial to form a loopback. The simulation result like below:
Thanks,
Best Regards,
Sheng
Hi,
please elaborate your question. UART receiver implementation in VHDL is more or less clear, how is it specifically related to loopback?
What's your problem with state machines?