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Altera_Forum's avatar
Altera_Forum
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12 years ago

UART and MODELSIM ALTERA (code attached)

Hi dears. I am trying to use a (slightly) modified version of the UART explained in a tutorial I've found, after reading some theory about. There is one UART entity which has two c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

just register them directly: 


signal rd_r : std_logic_vector(1 downto 0);
signal serial_rx_r : std_logic_vector(1 downto 0);
process(clk)
begin
  if rising_edge(clk) then
    serial_rx_r <= serial_rx_r(0) & serial_rx;
    rd_r <= rd_r(0) & rd;
  end if;
end if;

Then use rd_r(1) instead of the origional input "rd" and the same for serial_rx