UART and MODELSIM ALTERA (code attached)

Really I got 5 warnings about time restrictions during the compilation.

These warnings say that I need to specify some restrictions in a SDC file before compiling.

I am reading the following documentation from Altera:

White Paper - Understanding Metastability in FPGAs

http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf

14. Managing Metastability with the Quartus II Software

http://www.altera.com/literature/hb/qts/qts_qii51018.pdf

7. The Quartus II TimeQuest Timing Analyzer

Is that the way (TimeQuest Timing Analyzer) to correct the metastability using quartus II?

I attached a TimeQuest screenshot where it tells me that I need specify a SDC file. The first and the second process in the TimeQuest are checked as we can see in the screenshot.

Thanks.