UART and MODELSIM ALTERA (code attached)

You need to double register these 2 inputs using the 50MHz clock to prevent metastable events.

if serial_rx or rd have a rising edge the same time the 50mhz clock has a rising edge, then any registers sampling these signals will go meta stable, and so any other register may read it as 0 or 1 (depending on voltages). Using a double register prevents metastability, because the 2nd register will force and output of 0 or 1, and never meta-stable state.

You need this double register synchroniser or your internal logic may have meta-stable events.