Type do not match for port

May be caused by including ieee.std_logic_unsigned.

The other explanation is, that the component uses different port types. you didn't show it.

This is my new program. It's still error with yn and err

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
--Use ieee.numeric_std.all;
entity PhamNT is
  port(x_in,kd,ki,kp  :in std_logic_vector(15 downto 0):=(others => '0');
       clk            :in std_logic:='0';
       clk_op         :in std_logic:='0';
       yn             :out std_logic_vector (15 downto 0):=(others => '0')
	);
end PhamNT;
ARCHITECTURE structural OF PhamNT IS
  signal u,y         :std_logic_vector(15 downto 0):=(others => '0');  --x(n-1),Y(n-1)
  signal err         :std_logic_vector(15 downto 0):=(others => '0');
  signal go          :std_logic:='0';
  signal pl_go :std_logic:='0';
  signal	start 			: std_logic:='0';
  signal    mic_in 			: std_logic_vector(15 downto 0):=(others => '0');
  signal    z_out          	: std_logic_vector(15 downto 0):=(others => '0');
  signal    done           	: std_logic:='0';
  signal    u_in  	: std_logic_vector(15 downto 0):=(others => '0');
  component simp_cpu IS
  PORT(start : in std_logic;
       mic_in,kd,ki,kp  :in std_logic_vector(15 downto 0);
       z_out          :out std_logic_vector(15 downto 0);
       done           :out std_logic;
       clk            :in std_logic );
  END component;
  component dtdk_plant is
  port(x_in  :in std_logic_vector(15 downto 0);
       u_in  :in std_logic_vector(15 downto 0);
       go :in std_logic;
       clk   :in std_logic; 
       clk_op :in std_logic;
       err :out std_logic_vector(15 downto 0);
       yn    :out std_logic_vector(15 downto 0);
       pl_go :out std_logic);
  end component;
begin
U_Simp_CPU: simp_cpu port map (
							start	=> pl_go,
							mic_in	=> err,
							kd		=> kd,
							ki		=> ki,
							kp		=> kp,
							z_out	=> u,
							done	=> go,
							clk	=> clk_op
							);
							
U_dtdk_plant: dtdk_plant port map(
					x_in	=>	y,--x_in,
					u_in	=>	u,
					go		=>	go,
					clk		=>	clk,
					clk_op	=>	clk_op,
					err		=>	err,
					yn		=>	yn,
					pl_go	=>	pl_go
							);
end structural ;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_signed.ALL;
--Use ieee.numeric_std.all;
library lpm;
use lpm.lpm_components.all;
--use ieee.numeric_std.all;
entity dtdk_plant is
  port(x_in     :in std_logic_vector(15 downto 0):=(others => '0');
       u_in     :in std_logic_vector(15 downto 0):=(others => '0');
       go       :in std_logic:='0';
       clk      :in std_logic:='0'; 
       clk_op   :in std_logic:='0'; 
       err      :buffer std_logic_vector(15 downto 0);--:=(others => '0');
       yn       :buffer std_logic_vector(15 downto 0);--:=(others => '0');  
       pl_go    :out std_logic:='0'
	);
end dtdk_plant;
ARCHITECTURE structural OF dtdk_plant IS
signal u_ant              :std_logic_vector(15 downto 0):=(others => '0');
SIGNAL  mula1,mulb1       :std_logic_vector(15 downto 0):=(others => '0');
SIGNAL  mulr1             :std_logic_vector(31 downto 0):=(others => '0');
SIGNAL  adda1,addb1,addr1 :std_logic_vector(15 downto 0):=(others => '0'); 
constant fi               :std_logic_vector(15 downto 0) := "0110011001100110"; 
constant teta             :std_logic_vector(15 downto 0) := "0100000000000000";
signal cnt                :std_logic_vector(11 downto 0):=(others => '0');
signal aux                :std_logic_vector(15 downto 0):=(others => '0');
begin
mull: lpm_mult
    generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
		LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1)
	port map(dataa=> mula1,datab=> mulb1,clock=> clk,result=> mulr1);	
adder1: lpm_add_sub
	generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
    port map(dataa=>adda1,datab=>addb1,clock=> clk,result=>addr1);
GEN:block
begin
process (clk_op,go)
begin
if (clk_op'event and clk_op = '1') then 
  if go <= '0' then cnt <= cnt+1;
  else cnt<=X"000";  
  end if;
if cnt=X"000" then
   mula1 <= (u_ant);
   mulb1 <= (teta);
elsif cnt=X"001" then
   adda1 <=mulr1(30 downto 15);
elsif cnt=X"002" then
   mula1 <=(yn);
   mulb1 <=(fi);
elsif cnt=X"003" then
   addb1 <= mulr1(30 downto 15);
elsif cnt=X"004" then
   aux <= (addr1);
   u_ant <= (u_in);
elsif cnt=X"005" then
   adda1 <= (x_in);
   addb1 <= (-aux);
elsif cnt=X"006" then
   err <= (addr1);
   yn <= (aux);
   pl_go<='1'; 
elsif cnt=X"007" then
   pl_go<='0';
   if go='0' then cnt <= X"008";
   else cnt<=X"000";
   end if;
end if;
end if;
end process;
end block gen;
end structural;

I want to say a big thanks for FvM. You are expert in VHDL.

WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Incompatible modes for port err
WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error.
WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): Incompatible modes for port yn
WARNING: D:/Quartus/January_2011/Final 1/PhamNT.vhd(75): A use of this default binding for this component instantiation will result in an elaboration error.

At first sight, the buffer type has been changed to out in the component prototype. Not allowed with older VHDL standards.

thanks. I's true

Dear FvM

Could you help me? My project is totally stop :cry:

A := RF(CONV_INTEGER(fld_a));

VARIABLE A           :std_logic_vector(15 DOWNTO 0):=(others => '0');

This problem I met when i worked with Modelsim. It still work well with Quartus