Type do not match for port

Dear FvM

Sometime I run my project by ModelSim, some component are not bound. When it runs in Quartus, it's still ok. I don't understand this error. Do you know this error?

Thanks

This is warning in modelsim.

--- Quote Start ---

# Loading work.tb_cpu(structural)

# ** Warning: (vsim-3473) Component 'lop1_a' is not bound.

# Time: 0 ns Iteration: 0 Region: /tb_cpu File: D:/Quartus/January_2011/Final 1/Test_bench.vhd

# ** Warning: (vsim-3473) Component 'u_simp_cpu' is not bound.

# Time: 0 ns Iteration: 0 Region: /tb_cpu File: D:/Quartus/January_2011/Final 1/Test_bench.vhd

--- Quote End ---