Trying to test Filter using NCO Megafunction and Signal Tap Analyzer?

Hi,

I am not sure about your tool's features but I doubt it will generate synthesisable testbench which is rarely considered by design methodology as it wastes memory and is usually temporary.

Generally you can add to any project one test module consisting of one ram for stimulus input (fixed in mif or editable in memory editor) and another ram for reference output(again fixed in mif or editable) then you can use it to verify various modules within your project. The module will have a bit of logic to align and compare output with reference generating a flag. This is very useful if you don't have software to help you. Once project is signed off, you may remove the test module.

clock is the actual physical clock you use to run your logic. sampling rate is the rate of a given data stream.

depending on your fortunes, the clock may be equal, less than or more than data rate. if clock is faster you may process more than one channel of data (if applicable). if your clock is lower you will need to split up your channel into say even/odd and process them accordingly, in this case there will be design dependency of even/odd...

Sampling rate of your signal is inherent in that signal you are given for example it could be 27Msps then you are free to choose your system clock. The easiest way is to use a clock = 27MHz then you process each sample per clock.

You may opt to use 54Mhz clock in which case you can process two channels(if you have two of them) of 27Msps; one channel per clock period sharing same one resource.

Additionally if you have one channel then you may process at double speed for resource sharing e.g. compute half of filter sum of products in one cycle and second half in second clock then add up both halves so you may use half multipliers.

If your clock is 13.5MHz then you need to double resource to process one channel into two subchannels (even/odd).

Normally if you have one data channel then there is no need to make your system clock any different from sampling rate unless you are short of resource.

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Let me put it this way. You want to filter your input signal, then what determines sample rate is the sample rate when that signal was or is converted in an ADC(originally, assuming no further up or down sampling is done) or it could be your signal is generated digitally (rather than ADC) i.e. playing an LUT in which case the sampling frequency is the clock frequency that reads LUT.

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No i'm still using NCO so the signal is generated digitally. The signal i have has a clock rate of 50Mhz, and a output frequency of 1Mhz. so does that mean it wud sample once every 50 clock cycles? i feel like the Multichannel explaination is too indepth and missing the point of my question.

Hi Dansong,

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No i'm still using NCO so the signal is generated digitally. The signal i have has a clock rate of 50Mhz, and a output frequency of 1Mhz. so does that mean it wud sample once every 50 clock cycles? i feel like the Multichannel explaination is too indepth and missing the point of my question.

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A 1MHz sinusoid generated at 50MHz clock rate using an NCO generates a signal that is analogous to sampling a 1MHz sinusoid with a 50MHz ADC. In this example, your sample rate and clock rate are the same.

You could design a digital filter that also runs at 50MHz clock rate, and its construction would look like the 'classic' form you see in the documents I sent you.

If your 'system design' called for sampling a real-world signal that had content only out to 1MHz, then a 50MHz ADC would oversample the signal (since the Nyquist rate is 25MHz), allowing an analog filter with a slow rolloff to be used. The signal could then be digitally filtered to reduce the sample rate to say 50/20 = 2.5MHz, or mixed to complex-baseband and digitally filtered to between -1.25MHz and 1.25MHz.

Why do this? Well, your signal now has a 'sample rate' of either 5MHz real-valued samples, or 2.5MHz complex-valued samples, and your FPGA can operate at 50MHz, i.e., 20x or 40x faster. Now you have 20 or 40 FPGA clocks per sample, so you can re-use FPGA logic, eg., a single multiplier can be used to perform 20 or 40 operations before the next sample is ready.

Do you see how the 'sample rate' of the data and the 'clock rate' of the FPGA can be different? Once the data is inside the FPGA, its 'sample rate' depends on the signal processing operations you apply to the data.

Cheers,

Dave