Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi,
I am not sure about your tool's features but I doubt it will generate synthesisable testbench which is rarely considered by design methodology as it wastes memory and is usually temporary. Generally you can add to any project one test module consisting of one ram for stimulus input (fixed in mif or editable in memory editor) and another ram for reference output(again fixed in mif or editable) then you can use it to verify various modules within your project. The module will have a bit of logic to align and compare output with reference generating a flag. This is very useful if you don't have software to help you. Once project is signed off, you may remove the test module.