New Contributor
New ContributorThe error that I was getting *WAS* when I was trying to run the EDA simulation library compiler, as it seems I needed to do that before I could simulate anything. I'm glad to know that the MAX 10 devices are referred to by their process size vs their product name. That piece of info definitely helps clarify some things. I did all of the things specified by the first link and that led to the errors I'm seeing from the "quartus/eda/sim_lib/mentor/fiftyfivenm..." files. Would this kind of error occur if there was something wrong in the license file? From everything I've read about verilog and protected IP, it seems vlog *SHOULD* understand what its trying to process, but it doesn't seem to know what `<protected> is?
The second link appears to point to a Japanese language website, which I get the translated directions from so hopefully I'm not missing anything there, but in my simple test case I have *NO* ip included from any of the Mega wizards.
When I try to do anything with Nativelink, nothing at all happens except I see "Successfully launched NativeLink simulation" with the command and the report file contains no messages. So I'm not sure where that is going wrong, but I *DO* see a "Nativelink Error" dialog box which tells me to check the report file, which, as mentioned, is empty.
Actually, there is ONE way I can get NativeLink to open. But when I try to load the module I was building (called simulation_test in this case), it ends up having 1014 errors in which several things are not defined (which seem to be related to the fiftyfivenm_...
I was able to collect 2 transcripts. One is from trying to run the sim_lib compile (transcript_1.txt). The second was from running Questa by running it AFTER compilation (there seems to be a checkbox for that). This at least seems to bring up the design in Questa, but it cannot simulate the design because it doesn't have several fiftyfivenm pieces which, as you pointed out before, is for the MAX10, so I would likely have to have those. I don't know where I would even find those files, or if I have to generate those.
The design is just two, two-input and gates with outputs being fed into an or gate. The original design didn't even have the inputs or outputs going to actual pins, just to see if I could simulate anything without specifically tying it to anything other than the FPGA chip itself, but that led to compile errors, so I connected the inputs to pins on my ARROW DECA board (old now for sure) and the single output to another pin. This let the design compile, but I can't simulate this in any fashion. I was able to add signal tap, and was able to get some things for that, but signal tap, nice as it can be, will mean I have to reprogram the FPGA every time before testing the design. I was hoping to at least do some basic design testing to make sure things worked. But so far, no matter what I've tried, nothing works as it always seems to result in needing files I either don't have, like these transcripts show, or files I can't include because they have encrypted IP which the tool seems not to understand.
I updated this to include a third transcript, which I shows what happens when I try to simulate something using the university path... (i.e. add a vwf file and simulate this way). Because I can't generate the sim_lib for the MAX10, I am guessing that is what is causing the errors in transcript3.txt.
