Forum Discussion
"fiftyfivenm_atoms_ncrypt.v" is the simulation model for the MAX10 device. Therefore, you may encounter an error even when simulating a simple component like an AND gate.
Have you tried launching the EDA Simulation Library Compiler?
This tool facilitates the generation of simulation libraries. You can find more information about it in the following link: [https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/mapIdTopics/jka1465596847489.htm]
Since you are using Quartus Standard, you can also try simulating using the Nativelink feature. Nativelink automatically compiles your design, Intel IP, simulation model libraries, and testbench. You can refer to this article for more details:
[https://www.macnica.co.jp/en/business/semiconductor/articles/intel/131009/]
Best Regards,
Richard Tan
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