Occasional Contributor
Super ContributorNo this is not how the static region works. The static region is exclusively the yellow in your first diagram and always will be. It cannot be "extended" into a PR partition. That's why it's static. The whole point of PR is that the static (yellow) logic remains the same always while the logic in a PR partition (like parent1 or parent2) can be reconfigured, either the parent and all of its children or individual children, leaving the parent logic (dark green in your third diagram) alone.
There's no such thing as static_top_lvl_2.qdb as you've labeled it. Yes, you could have the dark green parent logic contain just wires connecting between the static logic (yellow) and the child logic (white), but you can't just skip over the parent logic design to connect the children to the top. If you're going to do this, you might as well just have the children be 4 individual PR partitions without parents in between.
Occasional ContributorYou are right. Probably, I shouldn't label it as "static"_top_lvl_2.qdb.
But I still think this should be theoretically possible.
There should be a full bitstream generated from the step below.
If I load this bitstream, it should set the routing from the top level to the children level.
Then if I program parent1 with bit1, it should overwrite the routing from parent to children.
We can program parent2 with bit2_1 and bit2_2. bit2_1 and bit2_2 should not overwrite the routing from parent to children.
The final programmed FPGA device should look like below.
I am not sure whether such overwriting is supported in Quartus PR.
Super ContributorNo. Again, you can't have the top-level include the fence and logic of a lower-level partition. static_top_lvl_2.qdb is not possible unless parent1 and parent2 were not separate design partitions, but they need to be for HPR.
