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Trigger in: an input signal from an I/O pin or internal to design used essentially as "trigger 0", the first trigger condition looked at by the tool
Trigger out: output signal indicating that a trigger has occurred
RAM size: number of samples of captured data you want to store in on-chip RAM; the more samples and signals monitored, the more OCRAM required
segment size: divide up the captured data buffer into evenly sized segments, good for observing signal behavior in the design for a trigger that repeats
This is all documented here in volume 3 of the Quartus Prime handbook:
https://www.altera.com/products/design-software/fpga-design/quartus-prime/support.html You can get detailed training on this here:
https://www.altera.com/support/training/catalog.html?coursetype=online&language=english&keywords=signaltap As for your capture question, you just set up a basic AND trigger to capture data when the signal goes high. Look through the documentation and training for details.
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Thanks alot for your help
Honored Contributor
