Transmission with DE2-70 and the daughter board THDB-ADA

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What exactly is the problem? have you run this through a testbench?

Did you realise that logic generated clocks are usually a bad idea?

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I just load the program in the board (DE2-70), and I would like to get the signal after the loop, (board -> converter D-A -> converter A-D -> board). I'm not a pro of VHDL, and it's the first time I use SignalTap, and I never used a testbench :(

You think it is better to use just iCLK_50 rather than ClockR and ClockF ? I tried this because it was a proposition in precedent posts ...

Thanks for your help !