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CFabr1
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5 years ago

Translating to Verilog and compiling Maxplus2 .bdf examples

Hi all, I'm trying to translate to Verilog some Maxplus2 examples (in .bdf format) of TTL gates but I get some errors when compiling.I'm using Quartus 12.1 For example, this is the generated Verilo...
CFabr1's avatar
CFabr1
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5 years ago

Yes, I know.The problems is that I have all my schematics done in Kicad (some are very big) and translating them to Quartus would be a huge job also because the schematics entry in Quartus is not really user-friendly and intuitive.