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CFabr1's avatar
CFabr1
Icon for New Contributor rankNew Contributor
6 years ago

Translating to Verilog and compiling Maxplus2 .bdf examples

Hi all, I'm trying to translate to Verilog some Maxplus2 examples (in .bdf format) of TTL gates but I get some errors when compiling.I'm using Quartus 12.1 For example, this is the generated Verilo...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
6 years ago

Hi Caius,

You can actually use Quartus to do that, conversion from schematic to HDL (Verilog/VHDL).

Thanks,

Regards