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CFabr1's avatar
CFabr1
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6 years ago

Translating to Verilog and compiling Maxplus2 .bdf examples

Hi all, I'm trying to translate to Verilog some Maxplus2 examples (in .bdf format) of TTL gates but I get some errors when compiling.I'm using Quartus 12.1 For example, this is the generated Verilo...
CFabr1's avatar
CFabr1
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6 years ago

Thanks for reply.I tried in the past this plugin and found that the Verilog translation is not yet implemented, only VHDL is supported although still bugged according to the author.I attach a snapshot of what he said about.