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CFabr1's avatar
CFabr1
Icon for New Contributor rankNew Contributor
5 years ago

Translating to Verilog and compiling Maxplus2 .bdf examples

Hi all, I'm trying to translate to Verilog some Maxplus2 examples (in .bdf format) of TTL gates but I get some errors when compiling.I'm using Quartus 12.1 For example, this is the generated Verilo...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
5 years ago

You miight try this: https://github.com/efarres/KiCad-HDL

It has several netlist translator plugins for KiCad that can translate the intermediate XLST format to various other formats (verilog and vhdl in particular).

I have not used this translation tool in particular (but I do use KiCAD for PCB schematics). The generated verilog should be pretty vanilla format.