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CFabr1
New Contributor
New ContributorTranslating to Verilog and compiling Maxplus2 .bdf examples
Hi all, I'm trying to translate to Verilog some Maxplus2 examples (in .bdf format) of TTL gates but I get some errors when compiling.I'm using Quartus 12.1 For example, this is the generated Verilo...
CFabr1New Contributor
New ContributorMany thanks for suggestions and help, I'm now able to successfully compile.Last thing : is there a way to convert schematics drawn with EDA softwares (ike Kicad) to Verilog compatible with Quartus?I could draw schematics block in Quartus and then convert to Verilog but it's a pain.Thanks in advance.
