Traffic Light State machine example counter clock

Hi, I am fairly new to Quartus and Verilog having mainly a software background.

I was looking at the use of the state machine wizard in a YouTube Tutorial at

(259) How to create a State Machine with the Quartus State Machine Wizard - YouTube

The tutor showed how to use the State Machine wizard to implement a traffic light system.

The tutor quite rightly used a counter to signal different states depending on the counter value, I am however baffled how the counter was made to count up as no mechanism/code was shown which actually incremented the counter! The system nevertheless worked because the generated Verilog seemed to somehow have inferred the existence of a clock from seemingly thin air. Can somebody please enlighten me if the if anything like State Machine compiler makes some assumptions based on components naming conventions e.g. 'counter*' or something like that?

Many thanks.