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Altera_Forum's avatar
Altera_Forum
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13 years ago

To enable the any block

Hi,

I am using VHDL for FPGA board. I want to enable any block. But when I am not enable to block, the block still operates. Where am I doing wrong. The simple VHDL code is shown in below. Simulation result was atteched.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY b1 IS

PORT ( clk,en: IN STD_LOGIC;d_out: OUT std_logic_vector(7 downto 0));

END b1;

ARCHITECTURE serial OF b1 IS

BEGIN

PROCESS (clk)

BEGIN

IF (clk'EVENT AND clk='1') THEN

if en='1' then

d_out<="00000011";

end if;

end if;

END PROCESS;

END serial;

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You never give any other value do d_out in your code, so Quartus must decide it is better to optimize your code by permanently assigning "00000011" to d_out.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    thank you for your attention. I changed the code in below. Also, simulation result is shown in atteched file. In simulation, &#304;t is shown that as dig=0. Why?

    LIBRARY ieee;

    USE ieee.std_logic_1164.all;

    ENTITY b1 IS

    PORT ( clk,en: IN STD_LOGIC;d_out: OUT std_logic_vector(7 downto 0); dig: out integer range 0 to 10);

    END b1;

    ARCHITECTURE serial OF b1 IS

    BEGIN

    process(clk)

    begin

    IF (clk'EVENT AND clk='1') THEN

    if en='1' then

    dig<=7;

    d_out<="00000011";

    end if;

    end if;

    end process;

    END serial;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Well I don't know what the synthesizer does exactly, I'm just guessing. But as long as you keep en to 0, Quartus can do whatever it wants with dig and d_out and it will still be compliant with your description. If you put en to 1 it should change dig to 7.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Ok. Why dout is change while temp is not change for en='0'? Eventually, if d_out is changing, program is entering in 'if loop'. I am conjecturing it. Also, I created different project and I obtained same result. I tried in Verilog, Program correctly worked.

    module mEnable(

    clk,

    enable,

    c

    );

    input clk;

    input enable;

    output reg [1:0] c=2'd0;

    always @ (posedge clk) begin

    if(enable==1'b1) begin

    c<=2'b11;

    end

    end

    endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I changed the program and the program correctly work.

    LIBRARY ieee;

    USE ieee.std_logic_1164.all;

    ENTITY b1 IS

    PORT ( clk,en: IN STD_LOGIC;d_out: OUT std_logic_vector(7 downto 0):="00000000"; dig: out integer range 0 to 10);

    END b1;

    ARCHITECTURE serial OF b1 IS

    BEGIN

    process(clk)

    begin

    IF (clk'EVENT AND clk='1') THEN

    if en='1' then

    dig<=7;

    d_out<="00000011";

    end if;

    end if;

    end process;

    END serial;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I changed that d_out: OUT std_logic_vector(7 downto 0):="00000000";

    Thanks Daixiwen and Tricky.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Yes the difference between your VHDL and your Verilog implementation was that in the Verilog code you used an initial value for your signal, forcing the synthesizer to use this value when it starts and to change it to the second one when you assert en.

    If you try to use a pure VHDL simulator, such as Modelsim, on your first code, you would see that all the output signals would be in the state 'U', which means uninitialized. A synthesizer can't do that because the 'U' state doesn't exist on real hardware. The synthesizer must choose a '0' or a '1' as initial state.

    As for why dig was initialized with 0 and d_out with your final value, I guess it's because the Quartus synthesizer has a different way of optimizing integer and vector signals.