To enable the any block

Yes the difference between your VHDL and your Verilog implementation was that in the Verilog code you used an initial value for your signal, forcing the synthesizer to use this value when it starts and to change it to the second one when you assert en.

If you try to use a pure VHDL simulator, such as Modelsim, on your first code, you would see that all the output signals would be in the state 'U', which means uninitialized. A synthesizer can't do that because the 'U' state doesn't exist on real hardware. The synthesizer must choose a '0' or a '1' as initial state.

As for why dig was initialized with 0 and d_out with your final value, I guess it's because the Quartus synthesizer has a different way of optimizing integer and vector signals.