To enable the any block

thank you for your attention. I changed the code in below. Also, simulation result is shown in atteched file. In simulation, İt is shown that as dig=0. Why?

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY b1 IS

PORT ( clk,en: IN STD_LOGIC;d_out: OUT std_logic_vector(7 downto 0); dig: out integer range 0 to 10);

END b1;

ARCHITECTURE serial OF b1 IS

BEGIN

process(clk)

begin

IF (clk'EVENT AND clk='1') THEN

if en='1' then

dig<=7;

d_out<="00000011";

end if;

end if;

end process;

END serial;