Timing violation with Altera GPIO in DDR mode

I think I made a mistake with the settings of the PLL. I used -90° instead of 90° phase shift. With this and the assignments:

set_false_path -setup -fall_from [get_clocks virt_adc_clk] -rise_to \
[get_clocks iopll262|iopll_0|adc_clk]
set_false_path -setup -rise_from [get_clocks virt_adc_clk] -fall_to \
[get_clocks iopll262|iopll_0|adc_clk]
set_false_path -hold -rise_from [get_clocks virt_adc_clk] -rise_to \
[get_clocks iopll262|iopll_0|adc_clk]
set_false_path -hold -fall_from [get_clocks virt_adc_clk] -fall_to \
[get_clocks iopll262|iopll_0|adc_clk]

I cuttet the wrong transfers.

Now with 90° pase shift I also get slacks at the input registers.

I could not find the maximum achievable frequency for the LVDS DDIO GPIO with an Arria 10 10AS066H3F34I2SG. Where can I find it?

Please find the test design in the attachment.

Thank you for your help!