Timing violation with Altera GPIO in DDR mode

This is edge-aligned. I changed to your recommendations and now Quartus compiles the design. This will takes some hours.

create_clock -period "262.144 MHz" -name  virt_adc_clk -waveform {0.0 1.907}
create_clock -period "262.144 MHz" -name  {SAMPLE_CLK_1} {SAMPLE_CLK_1} -waveform {0.0 1.907}
 
derive_pll_clocks -create_base_clocks
 
set_input_delay -add_delay -clock virt_adc_clk -min -0.6             [get_ports {ADC_DATA[*]}] 
set_input_delay -add_delay -clock virt_adc_clk -min -0.6 -clock_fall [get_ports {ADC_DATA[*]}] 
 
set_input_delay -add_delay -clock virt_adc_clk -max  0.6             [get_ports {ADC_DATA[*]}]
set_input_delay -add_delay -clock virt_adc_clk -max  0.6 -clock_fall [get_ports {ADC_DATA[*]}]
 
set_false_path -setup -fall_from [get_clocks virt_adc_clk] -rise_to \
[get_clocks iopll262|iopll_0|adc_clk]
set_false_path -setup -rise_from [get_clocks virt_adc_clk] -fall_to \
[get_clocks iopll262|iopll_0|adc_clk]
set_false_path -hold -rise_from [get_clocks virt_adc_clk] -rise_to \
[get_clocks iopll262|iopll_0|adc_clk]
set_false_path -hold -fall_from [get_clocks virt_adc_clk] -fall_to \
[get_clocks iopll262|iopll_0|adc_clk]

Should I delete the -create_base_clocks? I thought I need it forc other PPLs.