Timing violation with Altera GPIO in DDR mode

Thank you for your answer.

I tried this:

create_clock -period "262.144 MHz" -name  virt_adc_clk 
create_clock -period "262.144 MHz" -name  {SAMPLE_CLK_1} {SAMPLE_CLK_1}
 
create_generated_clock 	-name {CLK262} \
								-source [get_ports {SAMPLE_CLK_1}] \
								-divide_by 1 \
								-multiply_by 1 \
								-phase 90 \
   							-duty_cycle 50.00 { iopll262|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0] }
													
derive_pll_clocks -create_base_clocks

and also this without phase shift:

create_clock -period "262.144 MHz" -name  virt_adc_clk 
create_clock -period "262.144 MHz" -name  {SAMPLE_CLK_1} {SAMPLE_CLK_1}
 
create_generated_clock 	-name {CLK262} \
								-source [get_ports {SAMPLE_CLK_1}] \
								-divide_by 1 \
								-multiply_by 1 \
   							-duty_cycle 50.00 { iopll262|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0] }
								
derive_pll_clocks -create_base_clocks

The violations are the same. For the appplication is no difference because we use the ADC AD9652 and we adjust the DCO by starting the system.