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Altera_Forum
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19 years ago

Timing Simulation

Hi everybody,

quite often i would like to simulate sub blocks of systems using postlayout simulation. Since these blocks represent only subdesigns, their I/O pins are never routed to a physical pin of the FPGA. However, i have to use them as if they are "real pins". To solve this problem, i always insert FF to register the incoming signal. But i am really interested if there is any other solution at this point. Can i tell quartus that these are no real I/O pins, even when i am doing a timing simulation. Thanks,Chistian

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    You can assign I/O to be Virtual Pins, and they won't get routed to the actual device I/O, and therefore shouldn't have long delays to/from the I/O. (I assume that's why you were registering them). The virtual pins were designed for the case of a sub-block needing more pins than the device requires, but I believe it should work for you.

    Just as a side note, I've seen a lot of designers getting away from timing simulation, except perhaps on the finalized design. The biggest problem is that it takes too long. They tend to do functional simulation for RTL errors and static timing analysis for timing errors. You do need to be more stringent about how you code, but the Design Assistant(Assignments -> Settings -> Design Assistant) can help with that. (Most timing issues aren't really caught by timing simulations anyway. The biggest issue is that timing simulations take so long, plus you have to do a full place and route. And if the place-and-route isn't on the final design, then it's going to change on your next compile.
  • Altera_Forum's avatar
    Altera_Forum
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    19 years ago

    Adding to Rysc's comment about simulation runtime and what he said in his last sentence:

    If you are doing timing simulation on a piece of the design to make the simulation run faster, then be aware that a compilation result on a piece of the design will probably have timing different from a compilation result on the entire design unless you are using the bottom-up incremental compilation flow to preserve the timing of the lower-level block. For that matter, every compilation result will probably have some timing differences because of variation inherent in how the Fitter works (related to the reason the Fitter has a setting called "Seed"). If the point is to check the timing, use static timing analysis (TimeQuest or the Classic Timing Analyzer).