Timing Simulation

You can assign I/O to be Virtual Pins, and they won't get routed to the actual device I/O, and therefore shouldn't have long delays to/from the I/O. (I assume that's why you were registering them). The virtual pins were designed for the case of a sub-block needing more pins than the device requires, but I believe it should work for you.

Just as a side note, I've seen a lot of designers getting away from timing simulation, except perhaps on the finalized design. The biggest problem is that it takes too long. They tend to do functional simulation for RTL errors and static timing analysis for timing errors. You do need to be more stringent about how you code, but the Design Assistant(Assignments -> Settings -> Design Assistant) can help with that. (Most timing issues aren't really caught by timing simulations anyway. The biggest issue is that timing simulations take so long, plus you have to do a full place and route. And if the place-and-route isn't on the final design, then it's going to change on your next compile.