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SKGR0's avatar
SKGR0
Icon for New Contributor rankNew Contributor
6 years ago

Timing requirements not met inspite of optimised design.

I have been using a design on Cyclone V device. I use Quartus Prime 16.1.2 for compilaiton. The resource and logic utilisation is not above 50 %. What I observe is the timing requirements is not m...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Can you provide the design or describe what part(s) of the design are failing timing and by how much? Can you provide your .sdc file? Are you using physical placement constraints such as Logic Lock regions? It's hard to help optimize a design without seeing the design itself.

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