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Altera_Forum's avatar
Altera_Forum
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14 years ago

Timing Not Being Constrained?

My problem is that my design passes timing closure no matter how I constrain it (well almost). In particular, if I constrain the output timing like this;

create_clock -name {real_clock} -period 10.0 [get_ports {real_clock}]

create_clock -period 10.0 -name virtual_clock

set_output_delay -clock virtual_clock -max 5.0 [get_ports}{my_output_pin}]

Where my_output_pin is driven by synchronous logic clocked by real_clock. What I'm finding is that the design passes timing closure no matter what value I choose for the output delay, 5.0 ns or 15.0ns.

I know that Quartus is "seeing" my sdc file. If I remove my clock grouping commands I get all kinds of violations. It seems like I'm missing something simple.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You didn't post your clock grouping commands. And your problem may very well relate to that...

    Ie, if you do something like

    set_clock_groups -group {real_clock .... } -group {virtual_clock ...}

    then the path from real_clock to virtual_clock is set as a false path. That is, it's not analyzed.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    OK, I tried to post as little as possible since I didn't want it to get too complicated. The clock grouping goes;

    set_clock_groups -asynchronous -group {real_clock}

    set_clock_groups -asynchronous -group {real_clocka}

    set_clock_groups -asynchronous -group {real_clockb}

    There's no reference to the virtual clock in my grouping. What you're saying is perhaps that's the problem?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    OK, I tried to post as little as possible since I didn't want it to get too complicated. The clock grouping goes;

    set_clock_groups -asynchronous -group {real_clock}

    set_clock_groups -asynchronous -group {real_clocka}

    set_clock_groups -asynchronous -group {real_clockb}

    There's no reference to the virtual clock in my grouping. What you're saying is perhaps that's the problem?

    --- Quote End ---

    Peruse the timing report and it will tell you what clock is being used to compute the clock to output delay. That is the clock you need to use for your constraint as well.

    Kevin Jennings
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    OK, I tried to post as little as possible since I didn't want it to get too complicated. The clock grouping goes;

    set_clock_groups -asynchronous -group {real_clock}

    set_clock_groups -asynchronous -group {real_clocka}

    set_clock_groups -asynchronous -group {real_clockb}

    There's no reference to the virtual clock in my grouping. What you're saying is perhaps that's the problem?

    --- Quote End ---

    Yes, that is the problem.

    The first command sets all paths between real_clock and all other clocks as a false path.

    The second and third to the same for real_clocka and real_clockb.

    You probably need something like this

    set_clock_groups -asynchronous -group {real_clock virtual_clock} -group {real_clocka} -groups {real_clockb}
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Good.

    Be very carefull when using set_clock_groups and set_false_path commands.

    You're telling the tool not to care about some paths; make sure you're not cutting more paths than you should.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    set_clock_groups is pretty safe as long as you don't use the special syntax of having only one -group. That tells it to cut the clocks in that group from all other clocks in the design without explicitly naming them, so it's an implicit cut. You should merge them:

    set_clock_groups -asynchronous

    -group {

    real_clk

    }

    -group {

    real_clkb

    }

    -group {

    real_clkb

    }

    This only cuts between clocks in different groups of the same command, but will not cut timing to any clocks not listed.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks. I actually followed your (wonderful) document on timing constraints fairly closely, but didn't fully understand the implications of the syntax of the set_clock_groups command as you prescribed it. Your explanation in this post makes it clear.