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SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing failure on auto assigned pins

Hello, In my design I have 3 output pins that show a timing violation in Timequest. Their location is locked by the "set_location_assignment" TCL command in the project's QSF file. Because the PC...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Could you share the design before and after the location assignment? To generate the design QAR file, click on Project > Archive Project > Archive


Thanks.

Best regards,

KhaiY


SKon1's avatar
SKon1
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Both designs are archived and attached.
The pins in question are:

P2_indv : AP6
P2_ind[0] : AN6
P2_ind[1] : AP8
P2_ind[2] : AL7
P2_ind[3] : AM7

According to the fitter report of both failing and non-failing designs - they're mapped to the same I/O locations.
The ONLY difference between the 2 attached designs is that the one that fails has the "set_location_assignment" constraint assigned to the above location while the one that passes doesn't have the "set_location_assignment" constraint (it's commented out from the QSF).

Thanks for your help.

  • SKon1's avatar
    SKon1
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Any news on this subject?

    Have you been able to see the problem I'm describing ?