Forum Discussion

CWarr1's avatar
CWarr1
Icon for New Contributor rankNew Contributor
5 years ago

Timing Designer Inter-Path-Competition in Nios sub-system

Timing designer is reporting 'Inter-Path-Competition' issues for my Arria-10 FPGA design. The path that is highlighted is between the Nios processor and its associated onchip memory. Since both modules are created and connected within Platform Designer, I can not see how to duplicate the specified nodes.
Can anyone suggest how I might resolve this error?
Thanks!

2 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Can you show the error? Timing info from the Timing Analyzer? Need more details here.

    I'm not sure what the "Timing Designer" is. Do you mean the Design Assistant and you're failing a rule or something?

    • CWarr1's avatar
      CWarr1
      Icon for New Contributor rankNew Contributor
      5 years ago

      Apologies - I meant Timing Analyzer, not Timing Designer!

      I will close this request and re-post with a corrected title