Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorTiming Constraints with PLL clock muxes
I feed the output of pll to internal fpga logic that drives an output pin. How to constrain the output with respect to the clock input of pll? I am able to constrain w.r.t the output of pll
SK_VAOccasional Contributor
Occasional ContributorI have ports for Cb1_clk,Cb2_clk and out_clk.
I think because of the PLL I am not able to constrain with respect to input clocks.
