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skyjuice88
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2 years ago

Timing Constraints in DCFIFO through LPM

DCFIFO if generated through IP catalog will have the associated SDC constraints as well (set_max_delay/set_min_delay, set_net_delay and set_max_skew). What about DCFIFO instantiated through LPM (ht...
Timing
skyjuice88's avatar
skyjuice88
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2 years ago

Hi Richard Tan,

The document that you pointed out refers to FIFO that is written through RTL inference. Can I confirm the same applies to LPM instantiation which is using the template provided by Quartus?

In Quartus --> Edit --> Edit Template --> Verilog HDL --> Intel Parameterizable Macros --> async_fifo