timing constraint

I've seen this occasionally asked for when doing something like over-sampling an input, e.g. the data comes in asynchronously and drives 4 registers all with different phases of the clock.

This is not easy to do. The set_max_skew constraint might help, but probably won't be correct. The fitter optimizes for setup timing first, i.e. it tries to get everything as short as possible. Then for hold timing or skew, it tries to add delay in the router. This is fine for hold, but is usually too course of a delay for situations like this. What often has to be done is hand-place the registers in LABs equidistant from the input pin. (Note that a LAB can only have 2 clocks, so in the case I mentioned they had to be spread across multiple LABs). That at least gets them close. The other thing I've seen done is the logic gets put into a partition, and so when you get a fit you like, you can set it to post-fit and lock down the placement and routing.

Can you explain what you're doing. What device and how much skew can you handle? If it's really loose, then it might be easy, but if you're trying do really low skew between data paths, it might not be possible.