Timing Closure issue in Stratix V

Hi,

I am compiling a basic NIOS system consisting of ITCM and DTCM ports. The target device is Stratix V. Its difficult to close timings with the NIOS sub system. Clock is 245.76 MHz.

The following optimization and synthesis settings are used.

set_global_assignment -name SMART_RECOMPILE ON

set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED

set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON

set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM

set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL

set_global_assignment -name FITTER_EFFORT "STANDARD FIT"

The TNS is about -0.454 nsec.

Could anyone suggest some guidelines for timing closure. Please be reminded that the tight coupling impose a restriction of a fixed one cycle read latency on the instruction and data memories.

Thanks in advance,