Altera_ForumHonored Contributor13 years agoTiming Closure issue in Stratix V Hi, I am compiling a basic NIOS system consisting of ITCM and DTCM ports. The target device is Stratix V. Its difficult to close timings with the NIOS sub system. Clock is 245.76 MHz. The fo...Show More
Altera_ForumHonored Contributor13 years agohi!! Have you tried to use the Quartus Design Space Explorer or changing the fitter seed!!
Recent DiscussionsTiming analysis - long combinational pathDocker image for Quartus Pro 26.1 missing ?Error (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10Agilex 5 – Critical HSSI Error in JESD204B Example DesignThe quartus license works with version 25.0 but not with version 17.0