Altera_ForumHonored Contributor13 years agoTiming Closure issue in Stratix V Hi, I am compiling a basic NIOS system consisting of ITCM and DTCM ports. The target device is Stratix V. Its difficult to close timings with the NIOS sub system. Clock is 245.76 MHz. The fo...Show More
Altera_ForumHonored Contributor13 years agohi!! Have you tried to use the Quartus Design Space Explorer or changing the fitter seed!!
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: