Timing Analyzer problem

Hello everyone,

First of all, I'm sorry about my poor English. I'm newbie. I have a cyclone III with 64Mb SD RAM. I have built a small project with jtag, sdram and some PIOs via SOPC tool.

After compiling the project, I've have some problem with Timing Analyzer. I've constrained the clocks (input clock and PLL clock) and also unconstrained inputs (set_input_delay). But when I've done the same thing with unconstrained outputs (set_output_delay), there are some timing problem on setup time (attached image).

Can anyone solve this problem? I'm very appreciated

Best regards!

https://www.alteraforum.com/forum/attachment.php?attachmentid=6379