timing analyzer : about inter-path competition

The short answer right off the bat is that you shouldn't use either assignment since you have very little control over how the software will adjust things in your design. Perform manual register/node duplication in your HDL code to have complete control over how the design is adjusted to fix the timing issue.

The slightly longer answer is that all assignments in the Assignment Editor are discussed in detail in the built-in help. From the help table of contents, look for the "Logic Options" section and you'll find this:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_duplicate_atom.htm

And unfortunately, I'm looking at it and you're right that the help doesn't define what the value should be! It actually is just the name you want to give to the duplicated node that you're creating. For max fanout, the value is the fanout limit. So if you set a value of 64 and the node has a fanout of 65, the node will be duplicated and one fanout will be moved to the duplicated node. There's no defined strategy for what value to pick for this value, so that's why it's recommended to do this manually in HDL.

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