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DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Timing analysis on EMIF block

Hi,

I am having a strange issue when doing timing analysis on my design. I am using the Intel external memory interface IP (emif) in my design and the timing analysis tool cannot recognize the user clock output of the emif block. Even the get_clocks command cannot find this user clock. Is there anything I need to do to the emif block to make the tool recognizing the user clock output? The tool can recognize all other clocks in my design except this one.

Thanks

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  • DNguy4's avatar
    DNguy4
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    i found some conflicts in the sdc file that confuses the tool. it is fixed now.

    Thank you for your help.

  • BoonT_Intel's avatar
    BoonT_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi can you share the details of the conflict here? So that it can benefit other that facing the similar problem. Thanks in advance.​

  • DNguy4's avatar
    DNguy4
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    BCT_Intel,

    when i generate the IP, the tool knows the frequency of the reference clock. If I create the reference clock clock in the top level sdc again, it get confused, even with the -add option. I remove the reference from the top level sdc and the tool is happy.