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DNguy4
Occasional Contributor
Occasional ContributorTiming analysis on EMIF block
Hi, I am having a strange issue when doing timing analysis on my design. I am using the Intel external memory interface IP (emif) in my design and the timing analysis tool cannot recognize the user...
DNguy4Occasional Contributor
Occasional ContributorBCT_Intel,
when i generate the IP, the tool knows the frequency of the reference clock. If I create the reference clock clock in the top level sdc again, it get confused, even with the -add option. I remove the reference from the top level sdc and the tool is happy.
