Forum Discussion

DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Timing analysis on EMIF block

Hi, I am having a strange issue when doing timing analysis on my design. I am using the Intel external memory interface IP (emif) in my design and the timing analysis tool cannot recognize the user...
DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

BCT_Intel,

when i generate the IP, the tool knows the frequency of the reference clock. If I create the reference clock clock in the top level sdc again, it get confused, even with the -add option. I remove the reference from the top level sdc and the tool is happy.